Codasip® L110 is a 32-bit RISC-V embedded processor, focused on small-area and low-power applications.
The core is highly configurable, allowing different area and performance levels, with optional support for standard RISC-V code size density extension.
It is also fully customizable, and, when used in combination with Codasip Studio, it enables an easy and no-risk way to add custom instructions.
32 Bit - Embedded RISC-V Processor Core
Overview
Key Features
- Best-in-class performance for small-area and low-power applications
- Delivering up to 50% improvements in performance per watt compared to similar cores in the market
- Smaller and more performant than other RISC-V alternatives
- Uses RISC-V standard extensions for area and code size reduction for additional power consumption reduction at system level
- Highly configurable and easy and quick to customize and verify
- High-quality pre-verified baseline excellent for further configurations and
- customization
- Easy to customize and verify thanks to Codasip Studio Fusion
- Customization is without risk, because the functionality of the baseline core is guaranteed
- Process compliant with ISO 26262 and ISO 21434
- Developed using HW development process certified by TÜV SÜD
- Development process certified for functional safety as well as cybersecurity
Benefits
- Ideal standard RISC-V IP for low area and low power applications, competitive in delivering performance per watt.
- Highly configurable with optional support for standard code size density extensions. Excellent base to add custom instructions to further improve power, performance, and area for specific target application
Block Diagram
Applications
- Embedded
Technical Specifications
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- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
- 32 bit - Compact RISC-V Processor Core
- 32 Bit - Embedded RISC-V Processor Core
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