IP Catalog > Processor IP > General Purpose Processor IP > Other > 32-bit Application Processor

32-bit Application Processor

Overview

The royalty-free BA25 is a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25 processor runs at high clock frequencies yet has a smaller silicon footprint than most competing application processors (e.g., over 1100MHz and from 145K µm2 in TSMC 28nm HPM, including the FPU, and excluding SRAMs).

The BA25 is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Beyond Studio™ Eclipse-based IDE, architectural simulator, and ported C libraries, RTOSs, and OSs.

The royalty-free, high-performance BA25 processor core is suitable as the main system processor in a multitasking environment and is a competitive choice for designs running full operating systems such as Linux or Android. 

Key Features

  • High Performance 32-bit CPU 
    • Seven-Stage Pipeline 
    • Out-of-Order Completion 
    • Sophisticated Branch Prediction 
    • Optional Floating Point Unit 
    • 2.51 Coremarks/MHz 
    • 1100+ MHz on TSMC 28nm HPM 
  • Efficient Power Management  
    • Dynamic clock gating and power shut off of unused units 
    • Software- and hardware-controlled clock frequency  
    • Wake up on tick timer or external interrupt 
  • Fast & Flexible Memory Access 
    • Separate Instruction and Data Caches and MMU  
      • AXI4 data & instruction buses (32-, 64- or 128-bit) with 4 GBytes direct addressable space on each bus 
    • Tightly coupled Quick Memory (QMEM) interface for fast and deterministic access to code and/or data 
  • Two-Level Cache and MMU 
    • L0 cache running at core frequency and L1 cache running at half the core frequency 
    • 1–16 Kbytes L0 caches, up to four-way set associative 
    • 32–512 Kbytes L1 caches, up to four-way set associative 
    • L0 MMU with up to 32 four-way associative entries 
    • L1 MMU with up to 2048 four-way associative entries 
  • Optional Integrated Peripherals 
    • Vectored Interrupt Controller  
    • Microcontroller peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI 
    • Memory controllers, interconnect IP, and more 
  • Easy Software Development  
    • Non-intrusive JTAG debug/trace for both CPU and system 
    • Complex chained watchpoint and breakpoint conditions 
    • BeyondStudio™ complete IDE for Windows or Linux under Eclipse 
    • Ported libraries and operating systems 

Block Diagram

32-bit Application Processor Block Diagram

Technical Specifications

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