3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
Overview
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
55nm
Related IPs
- LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- IBM 65nm LVDS Transmitter
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression