The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell. An adapter cell is included to utilize this oscillator with libraries based on the 1.8V pad ring bus structure.
The 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 3.3V Support: Power. That library contains the DVDD/DVSS power cells necessary for ESD protection, the POC and VREF cells, and a rail splitter to isolate the oscillator in its own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
3.3V 100MHz Oscillator IO Staggered Pad Set
Overview
Key Features
- 100 MHz Crystal Oscillator Features
- ? Wide frequency range – 1 MHz to 100 MHz using industry standard external crystals.
- ? Optimized for stability and minimum jitter
- ? Power-down mode
- ? Operates on core power only (VDD/VSS cells embedded)
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES, 22nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Pre-Silicon:
22nm
FDX
Silicon Proven: 22nm FDX
Silicon Proven: 22nm FDX