The 1.8V General Purpose I/O library provides bidirectional I/O,
isolated analog I/O, and a full complement of power cells along with
corner and spacer cells to assemble a complete pad ring by abutment.
An included rail splitter allows multiple power domains to be isolated
in the same pad ring while maintaining continuous VDD/VSS for
robust ESD protection.
? Programmable bidirectional GPIO
? Input-only buffer
? Isolated analog I/O
? Full complement of power, corner, and spacer cells
3.3V 100 MHz Oscillator I/O Pad Set
Overview
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 7nm
Maturity
Silicon Proven
Availability
Available Now
TSMC
Pre-Silicon:
7nm