2Gbps Low Power D2D Interface
Overview
Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard full rail-to-rail swing, or a custom low-noise pseudo-differential interface. RX cells have a weak pull-down feature.
Key Features
- Core Device: 0.8V
- I/O Device: 1.8V Standard
- Core: Uses SVT only
- BEOL: M8 and below
- PAD: Flipchip/Die to Die packaging only, no wire-bond option.
- Cell Dimension: 50um x 28.06um
- VDD: 0.8V±10%, 0.7V/0.65V
- Temperature: -40C to 125C
- Operational Bit Rate: 2GBps per signal (MAX is 3.5GBps over corners)
- ESD: ESD testing of the I/O will never occur directly, but we need to sufficiently mitigate die-to-die CDM stresses and assembly issues.
Deliverables
- Verilog Models for all I/O, behavioral, and stubs.
- LEF's
- CDL netlists for DRC and LVS
- GDS
- IBIS
- Liberty TIming Models
- User Guide and Documentation
Technical Specifications
Foundry, Node
12nm, 16nm
Maturity
Silicon-Proven
Availability
Immediate
Related IPs
- Low Power D2D Interface in TSMC 16nm FFC/FFC+
- <4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- AHB Low Power Subsystem - ARM Cortex M0
- OSC Crystal Oscillator Low Power Series
- Low Power PLL for TSMC 40nm ULP