2Gbps Low Power D2D Interface

Overview

Key Features

• Core Device: 0.8V
• I/O Device: 1.8V Standard
• Core: Uses SVT only
• BEOL: M8 and below
• PAD: Flipchip/Die to Die packaging only, no wire-bond option.
• Cell Dimension: 50um x 28.06um
• VDD: 0.8V±10%, 0.7V/0.65V
• Temperature: -40C to 125C
• Operational Bit Rate: 2GBps per signal (MAX is 3.5GBps over corners)
• ESD: ESD testing of the I/O will never occur directly, but we need to sufficiently mitigate die-to-die CDM stresses and assembly issues.

Deliverables

• Verilog Models for all I/O, behavioral, and stubs.
• LEF's
• CDL netlists for DRC and LVS
• GDS
• IBIS
• Liberty TIming Models
• User Guide and Documentation

Technical Specifications