Vendor: Lattice Semiconductor Corp. Category: Video Processing

2D Scaler

The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.

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Overview

The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible architecture supports a wide variety of scaling algorithms. The highly-configurable design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming video or bursty input video data. In-system input and output frame size update is possible on a frame basis.

Key features

  • Support for multi-color plane (RGB and YCbCr4:4:4), serial filtering
  • Dynamic input and output frame size updating
  • Supports multi-scaling algorithms
  • Configurable number of filter taps for Lanczos coefficient set
  • Configurable number of phases for Bicubic, Mitchell and Lanczos coefficient sets
  • Configurable pixel data width
  • Configurable coefficient width
  • Configurable parameter bus width
  • Selectable memory type for line buffer and coefficient memories
  • Option for sharing vertical and horizontal filter coefficient memories

Block Diagram

SCALER block diagram

Files

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Specifications

Identity

Part Number
SCALER
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Provider

Lattice Semiconductor Corp.
HQ: USA
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices ( PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices ( CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.
Contact Lattice Semiconductor Corp.

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is 2D Scaler?

2D Scaler is a Video Processing IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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