2D Scaler
Overview
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible architecture supports a wide variety of scaling algorithms. The highly-configurable design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming video or bursty input video data. In-system input and output frame size update is possible on a frame basis.
Key Features
- Support for multi-color plane (RGB and YCbCr4:4:4), serial filtering
- Dynamic input and output frame size updating
- Supports multi-scaling algorithms
- Configurable number of filter taps for Lanczos coefficient set
- Configurable number of phases for Bicubic, Mitchell and Lanczos coefficient sets
- Configurable pixel data width
- Configurable coefficient width
- Configurable parameter bus width
- Selectable memory type for line buffer and coefficient memories
- Option for sharing vertical and horizontal filter coefficient memories
Block Diagram
Technical Specifications
Related IPs
- 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- Bit Block Transfer 2D video accelerator
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- 2D Down-scaler (Customized to two input resolutions and two output resolutions)**
- 2D Up-scaler (Customized to two input resolutions and two output resolutions)**