2D FIR Filter
Overview
The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory. Its flexible architecture supports a wide variety of filtering operations on various Lattice device families. The highly parameterized design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in system via a simple memory interface.
Key Features
- Single color plane
- Single-rate, interpolating, and decimating filter configurations
- Input frame size set at compile-time
- Static or dynamic zoom and pan
- User-specified 2D convolution kernel
- Separable and non-separable kernel support
- Kernel symmetry optimization
- Updatable coefficient
Block Diagram
