25MHz to 200MHz Low Jitter Low Power PLL

Overview

CT20900 is a PLL providing 33, 66, 50 and 200MHz clocks based on a 25MHz reference clock. It comprises a Phase Frequency Detector with internal charge pump that detects the phase difference between the 25MHz reference clock and the divided by 8 version of the 200MHz clock generated by the Voltage Controlled Oscillator (VCO).

The loop includes a second order Low Pass Filter (LPF)

Key Features

Fully Differential Topology
Charge Pump 3rd order configuration
2nd order passive loop filter
Fin = 25MHz, Fout = 33, 50, 66 and 200MHz
Maximum Jitter < 50ps
Max current consumption = 2.3mA

Benefits

Easy portability

Block Diagram

Applications

Automotive Ethernet
Baseband Telecom

Deliverables

Datasheet
Integration guidelines
GDS2 and LVS Netlist
Footprint (.LEF)
Test Specifications

Technical Specifications

Maturity

Silicon Proven OnSemi ONC18 0.18um HV-CMOS technology

Availability

Available

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