IP Catalog > Security IP > Crypto Accelerator IP > Hash and HMAC Accelerator IP > 256-bit SHA Secure Hash Crypto Engine

256-bit SHA Secure Hash Crypto Engine

Overview

The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits.

Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for AMBA bus interfaces and integration with an external DMA are available as options.

The SHA-256 can be used in various applications for ensuring data integrity, and authenticity. Some examples are on-chip communication, electronic fund transfers, digital signatures, password storage, blockchain technology and data backup.

Key Features

  • NIST-Validated SHA-256 implementation compliant to FIPS 180-4
  • Input length up to (264 – 1) bits
  • High throughput:
    • 65 clock cycles per 512-bit input block
    • Over 10Gbps on modern ASIC technologies
    • Throughput scaling with multiple clock instances.
  • Small Silicon footprint: 15k-20k Gates
  • Easy integration & implementation
    • Fully synchronous, uses only the rising clock-edge, single-clock domain, no false or multicycle timing paths, scan-ready, LINT-clean, reusable design
    • Simple input and output interfaces optionally bridged to AMBA™ interfaces or integrated with a DMA engine.
  • Available in VHDL or Verilog source code format, or as a targeted FPGA netlist
  • Complete deliverables include test benches, C model, and test vector generator
  • Multiple times production-proven in ASIC and FPGA designs

Block Diagram

256-bit SHA Secure Hash Crypto Engine Block Diagram

Technical Specifications

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