24-bit Cap-less ADC 106 dB SNR low power and PLL-less 3 channels

Overview

The sADC-uLP-SW1.01 is a mixed (analog and digital) Virtual Component containing six mono ADCs, and additional functions offering an ideal mixed signal front-end for low power, fast wake-up and high quality audio applications. It integrate our PLL-feature which allows you to use the IP with an available frequency in your SOC and thus save an audio PLL.

Key Features

  • I2C and APB control interface
  • Embedded low noise voltage regulator for best resilience to power supply noise
  • Low BoM and capacitor-less input connection
  • High dynamic range for high quality recording in far-field applications
  • Fast wake-up suitable for the unique analog VAD WhisperTrigger-A
  • Ultra low power mode, ideal for battery powered voice first devices

Block Diagram

24-bit Cap-less ADC 106 dB SNR low power and PLL-less 3 channels Block Diagram

Technical Specifications

Foundry, Node
TSMC 22nm uLL
Maturity
Pre-silicon
TSMC
Pre-Silicon: 22nm
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Semiconductor IP