224G-LR SerDes PHY enables 1.6T and 800G networks

Overview

Key Features

• TSMC 3nm process
• Supports full-duplex 1.25 to 225Gbps data rates
• Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
• Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
• Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
• Low power with configurability for different channel reaches
• Beachfront-optimized floorplan allows north-south and east-west SoC edge placement
• Small area and low power is ideal for high port-density applications
• Beach-front optimized floorplan allows north-south and east-west SoC edge placement
• Comprehensive on-chip diagnostic features make system testing and debugging quick and easy

Block Diagram

Applications

• Communications
• Data Processing

Deliverables

• GDS II macros with abstract in LEF
• Verilog post-layout netlist and Verilog models of I/O pads, and RTL for all PHY modules
• Verilog models of I/O pads, and RTL for all PHY modules
• STA scripts for use at chip or standalone PHY levels
• Verilog testbench with memory model, configuration files, and sample tests

Technical Specifications