Vendor: Synopsys, Inc. Category: Single-Protocol PHY

200G and 400G Ethernet PCS IP

The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a …

Overview

The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of features that enable users to define an optimized PCS in products across a range of 400G/200G Ethernet applications. The Synopsys PCS IP is designed to work with Synopsys Ethernet MAC IP to deliver solutions for 200G & 400G Ethernet applications. The multi-channel, multirate PCS allows flexible use of the various lanes for different PMA interfaces. The IP also includes multiplexed Reed-Solomon Forward Error Correction (RS-FEC) functions for use by different channels at various speeds

Key features

  • Single port 400G/200G
  • Quad 200G
  • Octal 400G

Benefits

  • Complaint with the IEEE 802.3bs standard
  • 400G PCS available in single, quad or octal port supporting multiple 100G/50G/25G/10G SerDes lanes
  • 200G PCS available in single or quad port supporting multiple 100G/50G/25G/10G SerDes lanes
  • Designed to be used with Synopsys 400G and 200G Ethernet MAC IP for 400G/200G Ethernet systems
  • Supports RS-FEC function
  • Silicon proven
  • Integration tested with the DesignWare 400G/200G Ethernet MAC and 112G Ethernet PHY IP

Applications

  • High-Performance Networking
  • High-Performance Computing

What’s Included?

  • SystemVerilog RTL Source code
  • Verilog Testbench environment with example testcases
  • Scripts and constraints files for implementation tools like Spyglass Lint/CDC, DesignCompiler, etc.
  • IPXACT views for register maps
  • Documentation: Databook, Integration User guide and Release Notes

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
dwc_200g_400g_ethernet_pcs
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is 200G and 400G Ethernet PCS IP?

200G and 400G Ethernet PCS IP is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP