2 Gbps Rail to Rail LVDS receiver

Overview

065TSMC_LVDS_10 is LVDS receiver with rail to rail input range. EN_T enables 100 Ohm internal resistor. The CAL_T<1:0> adjusts 100 Ohm internal resistor, the design target is to compensate the resistance deviation. The VREF12 is input 1.2 V voltage reference. Pin IREF_RX to get current 20 uA reference from receiver bias. INP and INN are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.
The block is designed on TSMC CMOS 65 nm technology.

Key Features

TSMC CMOS 65 nm
1.2 V CMOS input and output logic signals
2 Gbps (DDR MODE) switching rates
Conforms to TIA and IEEE standards without hysteresis
Rail to rail input range
Optimized for pad-limited layout design
Portable to other technologies (upon request)

Applications

Point-to-point data receiver
Multidrop buses
Clock distribution
Backplane receiver
Backplane data receiver
Cable data receiver

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 65 nm

Maturity

Silicon proven

Availability

Now

TSMC

Pre-Silicon: 65nm G
Silicon Proven: 65nm G

Request Info