2.5G MIPI D-PHY in TSMC 22nm

Overview

The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specification for MIPI D-PHY rev1.2 with speeds up to 2.5 Gbps per lane in 28nm or 22nm logic process node, this ACTT Design IP of MIPI D-PHY supports DSI/DSI-2 and CSI-2 protocols.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.

Key Features

? Complaint MIPI D-PHY v1.2.
? Support up to 2.5Gb/s HS data transmission.
? Support one clock and up to 4 data lanes.
? Support ULPS.
? Support LP reverse transmission only data lane0.
? 80Mbps to 1.5Gbps data rate per lane without Deskew calibrations
? 1.5Gbps to 2.5Gbps with Deskew calibration support
? Max data rate up to 10Mbps in low power mode
? Resistance termination calibration
? Built-in self test function capable of producing and checking PRBS random patterns
? Data lanes polarity swaping supports
? 8 bits/16 bits PPI interface support
? Operating junction temperature: -40°C ~ +25°C ~ +125°C;

Applications

DSI/DSI-2 Host
CSI/CSI-2 Device

Technical Specifications

Maturity

Available on request

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2.5G MIPI D-PHY in TSMC 22nm

Overview

Key Features

Applications

Technical Specifications

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