2.4GHz ISM Band ADPLL

Overview

The Orca Systems™ ORC9010 is a synthesized or synthesizable low-power all-digital phase-locked loop (ADPLL) Digital IP designed for 2.4GHz ISM band IoT applications such as Bluetooth and satellite IoT. The IP is portable across semiconductor process nodes and can be optimized for various applications and for various carrier frequencies and modulations. The ADPLL digital IP is designed to integrate with customer provided LC-based digitally controlled oscillator (DCO), time-to-digital-convertor (TDC) and digital-to- time-convertor (DTC).

Key Features

  • 2.4 GHz ISM band ADPLL (sub-GHz and L-band IPs also available)
  • 16 MHz to 48 MHz CPU programmable reference frequency
  • Support for 4 DCO Capacitor Banks:
    • PVT (with lock indication, calibration)
    • ACQ (with lock indication, calibration)
    • TRK (with lock indication, calibration, and gear-shifting)
    • MOD (with calibration)
  • Configurable interface from TDC
  • Bluetooth radio channel hopping FSM (Optional)
    • Store/Retrieve calibration data and FCW per channel for
    • frequency/channel hopping
  • CPU Control Interface
  • FCW input to DCO with sub-0.1Hz resolution
  • Loop control:
    • FCW integer and fractional input
    • Modulation Input (two-point)
    • Loop Filter parameter input
  • Initial Calibration FSM:
    • PVT, ACQ, TRK, and MOD Capacitor Bank states & calibration
    • Fine control over ADPLL functions per state
    • Control of timers per state
    • Filter BW control per state
  • Tx and Rx Warmup Calibration FSMs:
    • Including invKdtc, invKtdc, and invKdco calibration
  • Companion Polar Transmitter IP (optional)

Applications

  • Bluetooth
  • Satellite IoT
  • Cellular IoT

Deliverables

  • Licensed as fully synthesized IPs
  • Optionally Licensed as synthesizable Verilog RTL
  • Full Documentation
  • Basic support provided for customer application
  • Design customization support available
  • C++ binary simulation environment available for system level simulation and bit-exact matching of the RTL with C++ models
  • Extended support available for DCO/TDC/DTC integration

Technical Specifications

Maturity
Proven
Availability
Now
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Semiconductor IP