2.0 RFFE Slave IP

Overview

The RF Front End (RFFE) control interface is defined to offer a common Interface for controlling RF front-end devices. Most commonly used Front-End devices include Power Amplifier, Low-Noise Amplifiers, Filters, Switches, Power Management Modules, and Antenna Sensors etc. These Functions can be residing in the same chip or in a separate chip. Mobile Radio communications is trending towards complex multi-radio systems comprising of several transceivers. The RFFE bus is usable in such configurations by supporting single one Master and one Slave configuration to Multi-Master with many slaves. It is designed to support existing 3GPP standards such as LTE, UMTS, HSPA, EGPRS.

RFFE is a 2 wire serial interface and utilizes a relatively high bus frequency of 26MHz and Timing accurate trigger mechanisms to allow control of timing critical functions.

Key Features

Compliant with MIPI RFFE Specification 2.0
Delivered in Reuse Methodology Manual (RMM) compliant Verilog
RTL format
Optionally delivered as a physical design
Small footprint
Up to 15 Devices can be connected per RFFE bus
Low pin count on RFFE interface (SCLK and SDATA)
Low EMI
Low power consumption
Configurable RFFE clock speed of up to 26 MHz
Half speed read access for slow Slaves
VIO enable/disable for each slave on RFFE bus
Supports register 0 write, Register read register write
AHB Bus support for register configuration using programmed IO

Block Diagram

Deliverables

IP Deliverables for Digital Core

Verilog HDL of the IP Core
User guide
Gate count estimates available upon request
Synthesis scripts
Simulation environment including test bench, BFM’s, and exhaustive test suite

IP Deliverables for Physical Design

GDS-II Database
LVS Netlist
Physical Abstract Models (LEF)
Timing Models (LIB)

Technical Specifications

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