This macro-cell is a low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology.
The circuit generates 7 × NMOS 16nA current branches and 1 × NMOS 8nA branch. The current bias is temperature compensated using the PTAT thermal coefficient (TC) of an integrated resistor. The core is easily retargeted to any other CMOS technology due to high portability architecture.
16nA Resistive Current Bias - Low Voltage (1.0V), Low Power (360nW @ 1.2V) Silterra 0.18 um
Overview
Key Features
- Low power current bias
- Low TC
- Ibias=15.5nA ±10% (without trimming)
- Current consumption around 300nA in active mode
- Flexible voltage operation: 1.0V–2.0V
- Enable control
- Indicative area: 0.0072mm2
Block Diagram
Applications
- Passive/active RFID tag ICs
- Battery powered equipment
- Energy Harvesting ICs
- Hearing Aids
Deliverables
- Datasheet/Integration Guide
- HDL Model
- Flat GDSII database/LVS netlist
- Customer Support
Technical Specifications
Foundry, Node
Silterra 0.18 um
Maturity
Silicon Proven
Silterra
Silicon Proven:
180nm
Related IPs
- 15.5nA Current Bias with Enable - Ultra Low Voltage (0.9V), Ultra Low Power (50nW) Silterra 0.18 um
- 17nA Current Bias with Enable - Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V) TowerJazz 0.18 um
- ULP Bandgap Reference - Ultra Low Current (150nA) Silterra 0.18 um
- Low Power 12bit 640Msps silicon proven High performance Current Steering DAC IP Core
- 6MHz ±1% PVT 3.3V Low Power Oscillator in Silterra 0.18um
- Ultra Low Power AI core