16 to 64 MHz Phase-Locked Loop
Overview
130GF_PLL_01 is a ring VCO based phase-locked loop frequency with 16-64 MHz CMOS compatible output clock and fine frequency resolution thanks to the embedded delta-sigma modulator (DSM). The IP consists of a ring voltage controlled oscillator (VCO) with multiple sub-bands and sub-band autoselection system (SAS), a programmable N feedback divider (÷N) controlled by DSM, a digital phase-frequency detector (PFD) with a lock detector (LD), a charge pump (CP) with internal loop filter, a power management unit (PMU), and a programmable C clock divider (÷C).
Key Features
- Global Foundries BCD 130 nm
- Power supply from 4.5 to 5.5 V
- Operating temperature -40…+125 °C
- Low current consumption: up to 1 mA
- Reference frequency 32 MHz
- Output frequency from 16 to 64 MHz
- RMS jitter less than 35 ps
- PLL area 0.2 mm2
Applications
- Digital circuit clocking
- Clock for analog sensors
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
GlobalFoundries BCD 130 nm
Maturity
silicon proven
Availability
Now
GLOBALFOUNDRIES
Pre-Silicon:
130nm