The VA04D is a 16 state tail-biting error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed to decode the DVB-S2 or DVB-S2X standard rate 1/5 tail biting convolutional code.
16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder
Overview
Key Features
- 16 state (memory m = 4, constraint length 5) tail biting Viterbi decoder
- Rate 1/5 (inputs can be punctured for higher rates)
- Optional or standard DVB-S2/DVB-S2X code polynomials
- Data length K from 4 to 32 bits
- Up to 382 MHz internal clock
- Up to 46 Mbit/s decoding speed (K = 16)
- 6-bit received signed magnitude data
- 1315 6-input LUTs
- Asynchronous logic free design
- Free simulation software
- Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.
Deliverables
- All Licenses
- Xilinx VHDL Core
- Test vector generator
- ASIC License
- VHDL ASIC Core
- C++ bit/cycle exact simulation model
Technical Specifications
Availability
Now