16-bit General-purpose Fixed-point DSP Core, ADSP-218X Fully Compatible plus Enhancements

Overview

The WSP1600 DSP core is a high-speed scalar (one instruction per clock cycle) 16-bit fixed-point Digital Signal Processor optimized for communications, consumer electronics, multi-media, and other high-speed signal processing applications.

The WSP1600 DSP core combines the popular ADSP-218X architecture (3 Computational Units – ALU, MULT/MAC, Shifter, a Program Sequencer, 2 Data Address Generators, 2 DMA Ports, 2 Serial Ports, a Programmable Timer, Flag I/O, General Purpose I/Os, extensive Interrupt capability, IO space registers and on-core Program Memory (PM) and Data Memories (DM)) and WinStream's own Special Feature Enhanced Mode, which includes hooks for adding new instructions and additional banks of the Register File. The WSP1600 DSP core also features an extra set of I, M, L registers for the Data Address Generators as well as powerful MIN & MAX instructions. Similar to the PM, the DM in the WSP1600 core is implemented with Synchronous Dual-Access capability to allow both instruction and DMA triggered access to take place in the same cycle.

The control needed for the enhance features and functions is achieved by standard ADSP-218X instructions and thus requiring no changes to the standard ADSP-218X compiler, assembler, or development environment.

Key Features

ADSP-218X Fully Compatible Architecture
- Fully Compatible Instructions (execution and timing).
- Fully Compatible Interrupt Timing.
- On-core 16Kx24 PM and 16Kx16 DM.
- YES, PM can store both code and data just like ADSP-218X.
- 16-bit ALU.
- 40±16x16 MAC.
- 32-bit Shifter.
- Two Data Address Generation Units (DAG).
- IDMA and BDMA ports.
- Single Cycle Execution.
- Zero Overhead Looping.
- Two Serial Ports.
- Programmable Timer.
- General Purpose I/Os.
- Interrupt and Power-Down.
Other Enhancement
- Separate BDMA Port and IO Space.
- Synchronous Dual-Access (within one cycle) design for both PM and DM.
- One extra set of I, M, L Address Generator registers for more efficient Context Switching.
- Powerful Min, Max Instructions.
- Hooks for larger Register File.
- Hooks for Instruction Set Extension.
- 24-bit IDMA Port.
- Easily configurable PM and DM sizes (can go beyond standard 16K each).
- Expanded I/Os for easy embedding in SoC designs.
- Dynamic Frequency Change.
- 3 Design Patents.

Benefits

FULLY compatible to ADSP-218X
- All standard ADSP-218X application codes run on it.
FULLY synchronous and synthesizable design
- ASIC as well as FPGA implementation is straight-forward and proven.
Optimized for easy embedding in SoC designs
- All I/Os are expanded (not multiplexed).
- PM and DM sized are easily configured (changed) and optimized for target applications.
Enhanced for more efficient coding and lower power operations
- For the same application, WSP1600 code is expected to be smaller than the ADSP-218X code.
Most optimized Mult/MAC design
- Small, fast, and all Mult/MAC instructions complete in one cycle.
High-Speed non-pipelined design
- Purely scalar design (1MHz = 1MIPS).
- ALL instructions complete in one clock cycle with NO exceptions.
- Very small gate count.
- 125+ MHz easily achieved in 0.25um.

Deliverables

Synthesizable Verilog source code
Synthesis scripts
Test Bench
Test suites
Documentation

Technical Specifications

Foundry, Node

Any Std Cell based ASIC Design Environment

Maturity

Silicon-proven, ASIC-proven, FPGA-proven

Availability

Now

SMIC

Pre-Silicon: 180nm G

TSMC

In Production: 180nm G , 250nm G
Pre-Silicon: 250nm G
Silicon Proven: 250nm G

UMC

In Production: 250nm , 350nm
Pre-Silicon: 250nm , 350nm
Silicon Proven: 250nm , 350nm

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