16/32-bit Microprocessor

Overview

The D68000-CPU32+ soft core is binary-compatible with the industry standard 68000’s CPU32+ version of the 32-bit microcontroller. The D68000-CPU32+ has a 32-bit data bus and a 32-bit address data bus. It is code compatible with the 68000’s CPU32+ (version of MC68020). The D68000-CPU32+ has an improved instruction set, which allows program execution with higher performance than the standard 68000 core. It contains a built-in DoCD-BDM debugger interface. The D68000-CPU32+ is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.

Key Features

Software compatible with industry standard 68000’s CPU32+ (68020 version)
DoCD-BDM on-chip debugger as in CPU32+
VBR register
32-bit data and address registers
16 addressing modes:
- Direct:
  - Data register direct – Dn
  - Address register direct – An
- Indirect:
  - Register indirect – (An)
  - Post-increment register indirect – (An+)
  - Pre-decrement register indirect – (-An)
  - Register indirect with offset – (d16,An)
  - Indexed register indir. with offset – (d8,An,Xn)
  - Indexed register indir. with offset and base displacement – (bd,An,Xn)
- PC relative:
  - with offset(d16,PC); with index and offset – (d8,PC,Xn)
  - with index offset and base displacement – (bd,PC,Xn)
- Absolute data:
  - Absolute short (.W)
  - Absolute long (.L)
- Immediate data:
  - Immediate – #data
  - Quick immediate – #n
- Implied
5 data types supported:
- bits, BCD
- bytes, words and long words
Arithmetic Logic Unit includes:
- 8,16,32-bit arithmetic & logical operations
- 16×16, 32×32 bit signed and unsigned multiplication
- 32/16, 32/32, 64/32 bit signed and unsigned division
- Boolean operations
Interrupt controller:
- 7 priority levels interrupt controller
- Unlimited number of virtual interrupt sources
- Vectored and auto-vectored modes
- Format $0, $2, $C exceptions support as in CPU32+
Memory interface includes:
- Up to 4 GB of address space
- 32-bit data bus
- Asynchronous bus control
M6800 family synchronous interface
3- and 2- wire bus arbitration
Supervisor and user modes
Fully synthesizable, static synchronous design with no internal tri-states

Benefits

Rapid prototyping and time-to-market reduction
Design risk elimination
Development costs reduction
Full customization
Global sales network
Technology independence
Professional service
Getting a sillicon proven IP

Block Diagram

Deliverables

HDL Source Code
Testbench environment
- Automatic Simulation macros
- Tests with reference responses
Synthesis scripts
Technical documentation
12 months of technical support

Technical Specifications

Availability

now

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