14bit 3.2Gsps High Speed Sigma Delta ADC IP Core
Overview
High performance, 14-bit resolution, 3.2Gsps sample rate Mixed-signal Sigma Delta IP, nodes up to 28nm Silicon proven. Leading edge systems on chip (SoCs) for wireline networking, wireless communication, and automobile ADAS are made possible by these items. Our data converter (ADC and DAC) IP cores include resolutions ranging from 6 bits to 14 bits and sampling speeds ranging from a few MSPS to over 20GSPS.
Key Features
- Reduces noise and power consumption
- Increases ADC channel speed
- Provides accurate charge transfer without the need for calibration
- Relaxes op-amp gain, bandwidth, and offset requirements
- Simplifies high-performance analog designs
Benefits
- Available in 28nm nodes
- Excellent linearity
- Compact area
- Bandgap reference
- Silicon proven
- Sigma Delta
- Support for I/Q and array configurations
Applications
- 5G Wireless Infrastructure
- Automotive Ethernet
- Automotive LiDAR/RADAR
- Wireline Communication
- Wireless Communication
- Image Sensors
- Satellite Communication
Deliverables
- CDL netlists
- Liberty timings
- Verilog description
- A full datasheet
- An integration note
Technical Specifications
Maturity
In Production
Availability
Immediate
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