14-Bit 150MS/s 1.2V/3.3V 250mW ADC, CMOS 130nm
Overview
The nSAD_TS130M_3V3_1V2_AD14b150M is a 150MS/s, 13 ENOB, high-precision pipeline AD converter designed on the TSMC 130 M technology. Built around a fully-differential pipeline converter and a digital error correction circuitry, it consumes 295mW on silicon, reaching an energy efficiency of 240fJ/conversion-step. A low noise input buffer is provided for easier interfacing with your analog/RF front-end.
Key Features
- TSMC 130nm 1.2V/3.3V CMOS process
- Dual 3.3V/1.2V supply for highest linearity
- 20 to 150 Mspls/s scalable sampling rate
- 1 to 4 Vpp_diff selectable input dynamic range
- Up to 150MHz input buffer signal bandwidth
- DNL = ±0.5 LSB typ., INL = ±1 LSB
- SNR = 80dBFS @ Fin = 10MHz and 150MS/s
- SFDR > 86dBc @ Fin = 10MHz and 150MS/s
- Fully internal reference voltage generator and bias circuitry
- Proprietary architecture enhancements allowing very high conversion efficiency
- less than 1.3 mm2 core area including input buffer, reference generator and biasing
- Power down mode
Block Diagram
Technical Specifications
Foundry, Node
TSMC 130nm MM
Maturity
Available on request
TSMC
Pre-Silicon:
90nm
LP
,
130nm
G
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