14-bit 1-channel 100/125 MSPS pipeline ADC

Overview

The high-speed 14-bit ADC employs a high-performance differential pipeline architecture.
The ADC consists of a core ADC, LVDS clock receiver, reference voltages and currents circuit. The ADC requires 1.62 ÷ 1.98 V analog supply and 0.9 ÷ 1.1 V, 1.62 ÷ 1.98 V digital supply voltages.
This ADC supports standby mode which allows state with minimum power consumption. There is also the ability to configure the operating modes of the ADC with digital registers: register ref<3:0> controls the differential reference voltages, register ish<3:0> adjusts current of the sample and hold, register iadc<3:0> adjusts current of the core ADC.

The device is manufactured on TSMC 90 nm MS CMOS technology.

Key Features

TSMC 90nm MS CMOS
14-bit pipelined ADC
Single channel
100/125 MSPS conversion rate
Different power supplies for digital (1 V and 1.8 V) and analog (1.8 V) parts
Low standby current <10 uA
Low power dissipation 506 mW
Spurious-free dynamic range 73 dB
Portable to other technologies (upon request)

Applications

Optical networking
Test equipment
Portable ultrasound and digital beam-forming systems
Telecommunication systems
High quality imaging video systems

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 90 nm

Maturity

Silicon proven

Availability

Now

TSMC

Silicon Proven: 90nm G

Request Info