12bit 1Msps low power SAR ADC IP core
Overview
12-bit successive approximation Analog-to-Digital Converter (ADC) is designed for high-performance applications. Utilizing 28FDSOI technology with process options including 6 Metal (5+1), 8 Metal (6+2), and 10 Metal (6+2+2), this ADC achieves exceptional performance while maintaining a compact silicon footprint. With a parallel 12-bit output, this ADC offers a conversion time of 1 µs and a sampling frequency of 1 Msps, making it suitable for applications requiring fast and accurate analog-to-digital conversion. In terms of performance, the ADC delivers exceptional accuracy with Integral Non-Linearity (INL) of less than ±2 LSB and Differential NonLinearity (DNL) of less than ±1 LSB, ensuring precise conversion of analog signals into digital data. Overall, this ADC offers high-performance analogto-digital conversion in a compact and efficient package, making it ideal for a wide range of applications including industrial automation, medical imaging, and telecommunications.
Key Features
- 12-bit Parallel Output.
- Conversion time/Sampling frequency = 1 us/ 1Msps
- CLOCK REQUIREMENT: 2 MHz- 20 MHz
- SUPPLY REQUIREMENT: 1.8 V Analog/1.0 V Digital
- PERFORMANCE PARAMETERS:
- -INL
- Typ= +/- 2 LSB
- Max= +/- 4 LSB
- -DNL
- Typ= +/- 1 LSB
- Max= +/- 2 LSB
- -EOB
- Typ= +/- 10 LSB
- Max= +/- 20 LSB
- -EOT
- Typ= +/- 10 LSB
- Max= +/- 20 LSB
- -ANALOG INPUT FREQUENCY
- Typ= 100 KHz
- SNDR (Fin=100Khz,Fs=1MHz)
- Min= 54 dB
- Typ= 60 dB
- Process option: 6 Metal (5+1),8 metal (6+2) and 10 Metal (6+2+2)
- TEMPERATURE RANGE: Min= -40, Typ= 25, Max= 125
- Silicon Proven in 28FDSOI
- Production Proven
Benefits
- Low area and low power
- Excellent linearity
- Compact area
Block Diagram
Applications
- Medical Application
- Ethernet
- Automotive
- Communication system
- Microcontrollers
- Sensors
Deliverables
- Detailed Datasheet
- Verilog behavior model (A) for simulation
- Liberty (db./.lib) for synthesis, STA, and equivalence checking
- CTL / CTLDB for DFT
- SPF (Standard Test Interface Language (STIL Procedure File) for ATPG
- LEF for APR
- CDL for LVS connection
Technical Specifications
Maturity
In Production
Availability
Immediate