12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)

Overview

SESAME BiV 40 LP a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use of a patented flip flop.

Key Features

  • No need for a voltage regulator
  • Cells designed with 3.3 V thick-oxyde transistors to support a wide operating voltage range from 3.3 V +/-10% to 1.1 V +/-10%
  • Custom characterization corners down to 1.1 V +/-10% can be provided
  • Ideal for always on clock islets (RTC) and always on functional islets (voice recognition)
  • Low dynamic power with ultra-low leakage
  • Leakage reduction of 1/700 for a 5,000 gates islet implemented with BIV at 3.3 V, compared to a conventional HVT library operating at 1.2 V
  • Higher density compared to HVT library combined with voltage regulator
  • 12-track cells
  • 7X gain in density for a 5,000 gates islet implemented with BIV at 3.3 V, compared to a conventional HVT library operating at 1.2 V
  • SoC Integration secured and simplified from 3.3 V to 1.1V
  • Selection of the optimal characterization corners to maintain speed, reliability and consumption at low voltage
  • Full set of high-low and low-high level shifters isolated or not

Technical Specifications

Maturity
Pre-silicon
TSMC
Pre-Silicon: 40nm LP
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Semiconductor IP