12-bit 2-channel up to 50 MSPS current steering DAC

Overview

180TSMC_DAC_07 is a 12-bit 50 MSPS dual current steering DAC contains two DAC cores, reference current, bandgap, configuration register. Core DAC is based on current steering architecture and contains control logic, current source, switches array and reference voltage. There are two operation modes: with external reference current and internal reference current, which independent from voltage supply, temperature and dependent from process variations of resistor. DAC has a feature of adjusting output current. A segmented DAC architecture and Q2 random walk algorithm are used. DAC requires: 3.0 ÷ 3.6 V analog supply, 3.0 ÷ 3.6 V digital supply, differential input clock signal with duty cycle 45 ÷ 55%. 12-bit 50 MSPS dual current steering DAC supports standby mode.

Key Features

TSMC CMOS 180 nm
Resolution 12 bit
Dual channel
Different power supplies for digital (3.3 V) and analog parts (3.3 V)
Sampling rate up 50 MSPS
Standby mode (current consumption <100 nA)
Power dissipation:

75.24 mW at 50 MSPS and 10 mA output current

Differential current output range from 5 mA to 20 mA
Spurious-free dynamic range:

87 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
88 dB at 50 MSPS and fin = 11.513 MHz and 10 mA output current

Signal-to-noise ratio:

70 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
70 dB at 50 MSPS and fin = 11.513 MHz and 10 mA output current

Signal-to-noise and distortion ratio:

70 dB at 50 MSPS and fin = 1.575 MHz and 10 mA output current
70 dB at 50 MSPS and fin =11.513 MHz and 10 mA output current

Die area 0.67 mm2
Portable to other technologies (upon request)

Applications

Wireless infrastructures
Broadband communications
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Signals and arbitrary waveform generators

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 180 nm

Maturity

silicon proven

Availability

Now

TSMC

Silicon Proven: 180nm

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