In data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, near-packaged optics, co-packaged optics or die-to-die. Power and area efficiency is critical in these use cases. The Cadence 112G-VSR PAM4 SerDes PHY provides optimized power, performance, and area (PPA) for short-reach to medium-reach applications at 1.25Gbps to 116Gbps data rates.
112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
Overview
Key Features
- 1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
- Power optimized for short-reach applications with configurability
- Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
- Beachfront optimized floorplan allows north-south and east-west SoC edge placement
- Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
- Enables 800Gbps networking with PHY and Controller solutions
Benefits
- Superior Power Efficiency: Ultra-low power optimized for short-reach applications and optical I/O
- Robust Performance: Mature DSP-based architecture providing extra performance margin beyond short-reach standard requirements
- Flexible Data Rates: 1.25Gbps to 116Gbps flexible data rates supporting ETH, OTN, CPRI, JESD, and proprietary protocol rates
- Standard Compliance: Compliant with IEEE802.3 and OIF 112G short-reach standards
Block Diagram
Technical Specifications
Foundry, Node
TSMC 6nm,7nm
Maturity
Silicon proven
TSMC
Silicon Proven:
7nm
Related IPs
- 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- 56G-LR Pam4 SerDes PHY
- 32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- 112G-ULR PAM4 SerDes PHY
- Ethernet PCS IP - Integrates MAC IP to a broad range of PHY and SerDes IP
- 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC