10Gbps Multi-Protocol PHY IP

Overview

The first IP for PCIe 3.1 with L1 sub-states support

The PHY IP is designed to deliver high eye-margin at low power for backplane application. Numerous auto-calibrated circuits, programmable state machines throughout the design for PHY performance tuning, and the LC tank PLL provide a low-power optimum performance design. PCIe low-power states are also optimized to reduce total system power. All standard power states are supported. The Cadence IP is engineered to quickly and easily integrate into any SoC, and to connect seamlessly with a Cadence or third-party PIPE 4.0-compliant controller. The IP is silicon-proven in multiple process nodes and has been extensively validated with multiple hardware platforms. The Cadence 10Gbps Multi-Protocol PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP

Key Features

Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
High-performance decision feedback equalization and adaptive CTLE
Available in X1 through X10 lane configurations
Bifurcation and inverse bifurcation support
f Automatic calibration of analog circuits and offset correction
LC tank PLL with a wide range of reference clock frequencies and SSC
Serial and parallel loop-back functions
On-chip eye and bathtub monitor
Configurable PMA/PCS parallel interface

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

Standard integration views: LEF abstract, timing views (.LIB), behavioral model (Verily), gate-level netlist, SDF, DRC, LVS, ANT reports, and GDSII layout and layer map
Synthesizable soft PCS with SDC
Complete documentation including user guide, integration guide, and programmer guide
High Volume Manufacturing (HVM) kit
Testboards available upon request

Technical Specifications

Foundry, Node

TSMC 28nm

Maturity

Silicon proven

TSMC

Silicon Proven: 28nm

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