100G Only 320-bit Ethernet MAC + PCS @ 312.5MHz Solution; 4x25

Overview

Key Features

• MAC Core Features
• Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.
• Implements 802.3bd specification with ability to generate and recognize PFC pause frames
• Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.
• Implements a 320-bit CGMII interface operating at 312.5 MHz for 100G EMAC
• Implements Deficit Idle Count (DIC) mechanism to ensure maximum possible throughput at the transmit interface.
• Implements logic for padding of frames on the transmit path if the size of frame is less than 64 bytes.
• Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention. Non PFC mode only.
• Pause frame generation additionally controllable by user application offering flexible traffic flow control.
• Support for VLAN tagged frames according to IEEE 802.1Q.
• Support any type of Ethernet Frames such as SNAP / LLC, Ethernet II/DIX or IP traffic.
• Discards frames with mismatching destination address on receive (Except Broadcast and Multicast frames).
• Supports programmable promiscuous mode to omit MAC destination address checking on receive EMAC.
• Optional multicast address filtering with 64-bit HASH Filtering table providing imperfect filtering to reduce load on higher layers.
• CRC-32 generation and checking at high speed using an efficient pipelined CRC calculation algorithm.
• Implements logic for optional padding removal on RX path for NIC applications or forwarding of unmodified data to the user interface.
• Discards runt frames (less than 64 Byte) at the core’s reconciliation sublayer.
• Implements logic for optional forwarding of the CRC field to user application interface.
• Implements logic for optional forwarding of received pause frames to the user application interface.
• Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).
• Status signals available with each Frame on the user interface providing information such as frame length, VLAN frame type indication and error information.
• Implements programmable internal CGMII Loop-back.
• Implements statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames.
• Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments.
• Implements a streaming user application interface. The application interface is designed as a 512-bit non-segmented (start of a new frame on next 512-bit word) interface operating at 312.5MHz.
• An interface wrapper is provided for applications that implement a segmented (start of new frame within same 512-bit word with 64-bit alignment) bus. In segmented mode, the 512-bit bus operates at @ 225MHz for 100Gbps.
• Implements memory-mapped host controller interface for accessing the core’s register file.
• PCS Core Features (Common)
• Implements 100GBase-R PCS core compliant with IEEE 802.3ba Specifications.
• Implements a 320-bit CGMII interface operating at 312.5MHz for 100G Ethernet.
• Implements 64b/66b encoding/decoding for transmit and receive PCS.
• Implements 100G scrambling/descrambling using 802.3ba specified polynomial 1 + x39 + x58
• Implements Multi-Lane Distribution (MLD) across 20 Virtual Lanes (VLs)
• Implements periodic insertion of Alignment Marker (AM) on the transmit path and deletion on the receive path
• Implements 66-bit block synchronization and Alignment Marker Lock machines as specified in 802.3ba specifications.
• Implements skew compensation logic in order to realign all the virtual lanes and reassemble an aggregate 100G stream (with all 64b/66b blocks in the correct order)
• Implements lane reordering to support reception of any virtual lane (VL) on any physical lane (PL).
• Implements BIP-8 insertion/checking per Virtual Lane on transmit/receive respectively.
• Implements Inter Packet Gap (IPG) Insertion/Deletion for Alignment marker and clock compensation while maintaining a minimum of 1 byte IPG.
• Implements programmable internal CGMII loop-back which directs traffic received from core's receive path back to transmit PCS.
• Implements Bit Error Rate (BER) monitor for monitoring excessive error ratio. In addition, the core implements various status and statistics required by the IEEE 802.3ba such as block synchronization status, AM lock status, lane de-skew and lane reordering status and BIP-8 error counters per virtual lane.
• PCS Core Features (CAUI-4 Option)
• Implements gear-box logic for Xilinx to convert 20 VLs of 66-bit blocks to 4 PLs of 160-bit data for line side CAUI-4 interface. The 160-bit interface operates at the transceiver reference clock of 161.1328125MHz.
• Implements gear-box logic for Altera to convert 20 VLs of 66-bit blocks to 4 PLs of 128-bit data for line side CAUI-4 interface. The 128-bit interface operates at the transceiver reference clock of 201.416015625MHz.
• Transceiver Wrappers for Xilinx GTY/GTZ transceivers and Altera GT transceivers.
• PCS Core Features (CAUI-10 Option)
• Implements gear-box logic for Xilinx to convert 20 VLs of 66-bit blocks to 10 PLs of 40-bit data for line side CAUI-10 interface. The 40-bit interface operates at the transceiver reference clock of 257.8125MHz.
• Transceiver Wrappers for Xilinx GTX/GTH transceivers and Altera GX/GS transceivers.

Technical Specifications