The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-Negotiation (25GBASE-KR).
The 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) is a Xilinx LogiCORE™ which has an optional FEC (forward error correction) and/or auto-negotiation protocol and link training allowing ultimate flexibility in your solution. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY over a backplane. The demand for 10G Ethernet is being driven in the data center as internet data traffic continues to grow. LAN application include Storage Area Networking (SAN), aggregation of 1G Ethernet links, and switch to switch links in the data center, equipment room or in different buildings.
NOTE: For UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
Overview
Key Features
- Designed to 10-Gigabit Ethernet specification IEEE 802.3-2012 clause 49, Forward Error Correction (FEC) clause 74, and Auto-Negotiation clause 73
- Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2012 clause 45
- Available under the Xilinx Project Core License Agreement
- Supports LAN mode only
- SDR XGMII interface connects seamlessly to the Xilinx 10G Ethernet MAC