10-Bit 100MS/s 1.8V 66mW ADC, CMOS 0.18µm
Overview
The nSAD_UM180M_1V8_AD10b100M is a 100MS/s, 9.5 ENOB, highspeed and low-power AD converter designed on the UMC 180 MM technology. Built around a fully differential proprietary time-enhanced pipeline converter and a digital error correction circuitry, it consumes 66mW on silicon, reaching an energy efficiency of 911fJ/conversion-step.
Key Features
- UMC 180nm 1.8V CMOS process with MIM capacitors (optional)
- Single 1.8V supply
- up to 100 Mspls/s sampling rate
- 2Vpp_diff input dynamic range
- DNL = ±0.5 LSB typ., INL = ±0.7 LSB
- Fully internal reference voltage generator and bias circuitry
- Proprietary conversion scheduling for lower power consumption
- only 66mW typical at 100Mspls/s
- 1.1 mm2 core area including reference generator, biasing and internal decoupling
- Power down mode
- SNR and SFDR figures
Block Diagram
Technical Specifications
Foundry, Node
UMC 180nm MM
Maturity
Silicon proven
TSMC
Pre-Silicon:
40nm
LP
,
90nm
LP
UMC
Silicon Proven:
180nm
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