10-bit 1-channel 100 MHz current DAC

Overview

The 10-bit dual high-speed DAC is based on current steering architecture, which provides high-speed conversion rate and good dynamic performance. DAC consists of three principal blocks: adjustable reference voltage and current generator, decoding logic, current source and output switches array. Device has a feature of adjusting output current and entering sleep mode, turning the device off. DAC requires 1.8 V analog and digital supply, and digital and analog ground to work properly. Pins dac[2:0] adjust DAC output current.
The device is implemented on technology SMIC EEPROM CMOS 0.18 um.

Key Features

SMIC EEPROM CMOS 0.18 um technology
Resolution 10 bits
100 MSPS update rate
High spurious free dynamic range performance up to 25 MHz output
Adjustable output current (from 1.8 mA to 2 mA)
Sleep mode (current consumption less than 200 nA)
Portable to other technologies (upon request)

Applications

Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Signals generators, arbitrary waveform generators

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

SMIC EEPROM CMOS 0.18 um

Maturity

Silicon proven

Availability

Now

SMIC

Pre-Silicon: 180nm EEPROM
Silicon Proven: 180nm EEPROM

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