1 to 50 MHz phase-locked loop frequency synthesizer
Overview
055TSMC_PLL_03 is a PLL frequency synthesizer that generates two clock signals in the range from 1 MHz to 50MHz. The synthesizer consists of one voltage-controlled oscillator (VCO) with internal LC circuit and automatic subband selection system; a digital phase frequency detector (PFD); a precision charge pump (CP) with integrated adjustable loop filter; a programmable divider of reference signal; a system of programmable feedback dividers controlled by a delta-sigma modulator (DSM) and output signal dividers.
Key Features
- TSMC CMOS 55 nm
- Output frequency range from 1 MHz to 50 MHz
- Reference frequency range from 5 MHz to 50 MHz
Applications
- Frequency clock generation
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 55 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
55nm
FL