1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)

Overview

eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Tier1network/storage/5G OEMs and major semiconductor companies. Our solution is also applicable to fastgrowing Al applications.

eTopus was among the first startup company to provide ADC/DSP-based 56Gbps SerDes IP for the emerging PAM4 signaling back in 2016. Our unique and patented DSP algorithms provide superior Bit Error Rates (BER) and robust Clock Data Recovery (CDR) from short to long reach interconnects with scalable power consumption.

eTopus provides a rich portfolio of mixed signal IP available including Analog Front-End, Analog-to-Digital, Digital-to-Analog converters for licensing in multiple process nodes.

Key Features

  • On-chip AC-coupled receiver eliminates on-board decoupling capacitors
  • Dual power supply rails further reduce system BOM cost
  • Low jitter full chip clock distribution architecture
  • Quad/Octal configurations per PLL with tight lane skew control
  • Integrated common PLL for quad/octal configuration minimizes power consumption
  • Layout supports north/south and east/west (escape routings and package stack-up guidelines provided)
  • Comprehensive BIST supporting PRBS testing of major standards
  • Pseudo Reed-Solomon Forward Error Correction (RSFEC) error analyzer provides multi-bit error analysis
  • Receive impulse response measurement for in-situ endapplication system integration

Benefits

  • Multi-protocol ePHY IP supports 1-56/112Gbps data rates
  • Low-Jitter Transmitter with 8-tap de-emphasis FIR
  • Adaptive receive equalizer scales from short to long range of
  • channel loss (10-35dB)
  • On-chip real-time monitor for channel quality and receive eye
  • measurement
  • Upgradable firmware for post-silicon extensible functionality
  • Support IEEE802.3bj/cd, InfiniBand EDR, and OIF CEI-25GLR/MR/SR/VSR Electrical Interfaces

Deliverables

  • System Deliverables
    • Software Development
    • Kit
    • Reference Board
    • IBIS AMI Model
    • CPM Power Model
  • Frontend Deliverables
    • Verilog Behavioral Model
    • Timing Libraries
  • Backend Deliverables
    • LEF
    • GDS
    • CDL
    • DRC & LVS reports

Technical Specifications

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Semiconductor IP