A TSMC 110nm Wirebond and Flipchip compatible I/O library with 1.2V/3.3V Fail-Safe GPIO, 3.3V I2C Open-Drain I/O, SPI and associated ESD.
This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this node. It features a 1.2V/3.3V GPIO with selectable drive strengths and optional internal 100K ohm pull up or pull down resistor and a selectable Schmitt trigger. The ODIO mode targets the official I2C standard at 3.3V. Cells for IO core power and ground with built in ESD are included. Thelibrary is enriched with feed through, filler, corner, and domain break cells to allow for flexible padring constructions. ESD design levels are 2kV HBM and 500V CDM.
Operating Conditions
| Parameter | Value |
| VDDIO | 1.2V, 1.8V, or 3.3V dynamic |
| Core VDD | 1.2V |
| Tj | -40C to 125C |
| MaxLoad | 75pF, 300pF ODIO |
Cell Size and Metal Stack
| Cell Size | Metal Stack | WB Pitch |
| 100x220um | 1P7M_6x1z | 140um single |
Library Cell Summary
| Cell Type | Feature |
| Supply/ESD | 3.V; 1.2V; GND |
| GPIO | 100MHz (75pF) |
| I2C ODIO | 3.3V |
| OTP | 3.3V programming gate cell |
| Break Cells | VDDIO, VDD |
| Filler Cells | 1um, 5um digital & analog |
