1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
Key Features
- Quad SerDes optimized for Fibre Channel and backplane applications
- Supports data rates from 1.0625/2.125 and 4.25 Gbps speeds
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution
- 8b/10b encoder and decoder
- High speed serial CML output drivers with internal 50 W terminations
- High speed serial CML input stage with internal 50 W terminations
- Auto-calibration termination
- Supports up to four levels of pre-emphasis on the serial output drivers
- Supports up to four levels of equalization at the serial inputs
- Comma Detect for character alignment
- Local serial loopback test mode
- Pseudo-Random (PRBS) pattern generator and error checker to support BIST
- Serial interface MDIO
- 1149.1 compatible JTAG port
- 1.0/1.8V ±5% supplies
- Power dissipation 125 mW/Ch
- TSMC advanced 90 nm CMOS process
- Portable to other processes
Technical Specifications
Foundry, Node
TSMC advanced 90 nm CMOS process
TSMC
Pre-Silicon:
90nm
G
Related IPs
- Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
- Quad 3.125/6.25 Gbps Backplane SerDes
- FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- Fibre Channel Link Layer Core
- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
- 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction