Toward an intuitive system design environment
Sandeep Dutta & Ramine Roane
embedded.com (May 3, 2016)
Advanced systems are becoming increasingly complex, forcing manufacturers to spend correspondingly greater time developing and debugging each device -- typically with little visibility into system-level interactions of multiple components. Visual System Integrator (VSI) is a unique tool that facilitates system design and integration by enabling designers to graphically describe their heterogeneous systems completely and accurately. Based on this description, the tool automatically generates drivers required for communication across standard interfaces. Consequently, architects and engineers can focus on their key differentiators rather than on designing and debugging standard data transport and device drivers. VSI is flexible enough to allow the user to extend or replace the implementation of any of the runtime components. In this article we explore the different aspects of this novel development environment, including hardware platform description, application development, as well as built-in runtime and trace facility.
Describing the Hardware Platform
The VSI Platform description environment accelerates platform creation and maintenance by providing an intuitive visual environment for the task, enabling system architects and even software developers to rapidly create and iterate on complex hardware platforms. Figure 1 below illustrates a platform composed of and FPGA board connected to an external host. Note that the user specifies which interfaces to elevate at system level.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Transactions in an OVM SystemVerilog Verification Environment
- ipPROCESS: A Usage of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi Project Environment
- Software Architecture for IP verification in Operating System environment
- System Verilog configurable coverage model in an OVM setup - concept of reusability
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS