Legacy RTL brought into system-level flow
(06/26/2006 9:00 AM EDT)
As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs.
Designers might hesitate to use ESL because of legacy RTL intellectual-property libraries that represent thousands of man-years of invested time. But legacy RTL IP can be the basis for new designs that leverage ESL methodologies.
Designers who have tried ESL design recognize that some parts of a design are more conducive to ESL while others are more efficiently implemented using established IP libraries. Typically, ESL is used to create new, differentiated system components; RTL IP is best for the obligatory nondifferentiated parts of the design.
Where do these two methodologies come together? Actually, they are different aspects of a holistic electronic-system design methodology.
ESL does not replace RTL design. Instead, the ESL design flow extends RTL flows into higher levels of abstraction, much as RTL design extends gate-level design.
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. Platform-based design is made more effective when it uses Spirit XML data books from the Spirit Consortium to describe the IP. These data books include configuration and validation information to help determine the processes that must be executed to integrate the block into a system-on-chip design.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Gbit interface forces analog IP into digital flow
- Transactional level as the new design and verification abstraction above RTL
- From Behavioral to RTL Design Flow in SystemC
- Accurate System Level Power Estimation through Fast Gate-Level Power Characterization
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems