High-Level Synthesis - Ready for prime-time?
Maneesh Soni, Texas Instruments, Inc., Jack Erickson, Cadence Design Systems, Inc.
EETimes (11/23/2010 7:51 PM EST)
For about two decades, hardware designers have been trying to use high-level synthesis (HLS) tools. The primary goal of high-level synthesis tools has been to increase design and verification productivity by raising the level of abstraction and by defining the architectures using less code. In addition, the idea is to also reduce complexity and the number of bugs introduced due to human-error, increase simulation speed, and facilitate exploration of alternative micro-architecture choices.
This article describes the work done at Texas Instruments (TI) to research the suitability of the latest generation of HLS tools for hardware design. Particularly, the analysis is focused on C-to-Silicon Compiler from Cadence Design Systems. The findings will interest RTL designers and architects who might be considering adoption of HLS tools, methodologies, and flows.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- How High-Level Synthesis Can Raise the Efficiency of Design Reuse
- High-level synthesis, verification and language
- The future is High-Level Synthesis
- Building a NAND flash controller with high-level synthesis
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems