How to exploit the uniqueness of FPGA silicon for security applications
By exploiting the silicon uniqueness of each FPGA device and extracting these "silicon biometrics", FPGAs can be used for new security-oriented applications not previously possible.
By Mandel Yu, Verayo
pldesignline.com (December 10, 2008)
FPGAs are used in place of ASICs for an increasing number of applications. Traditionally seen primarily as devices with programmable gates, FPGAs have progressively evolved since year 2000 into "platform" devices with many integrated system-on-a-chip features, including components such as Ethernet MACs, DSP engines, microcontrollers, clock management circuitry, I/Os with reconfigurable signaling standards and terminations, and facilities supporting Bitstream encryption to prevent reverse engineering of designs.
This article expands the application areas covered by FPGAs by introducing a new class of primitives called "Soft PUFs." By exploiting the silicon uniqueness of each FPGA device and incorporating a special circuit (using existing FPGA fabric) to extract these "silicon biometrics", FPGAs can be used for new security-oriented applications that were not previously possible.
Physical Unclonable Functions
Physical Unclonable Functions (PUFs) are circuits that extract chip-unique signatures based on semiconductor fabrication variations that are very difficult to control or reproduce. These chip-unique signatures can be used to identify chips (a form of "silicon biometrics"), and can be used to generate "volatile" cryptographic keys. These keys disappear when the device is powered off; they can be bit-accurately restored, with aid of error correction, on subsequent power-ups.
By Mandel Yu, Verayo
pldesignline.com (December 10, 2008)
FPGAs are used in place of ASICs for an increasing number of applications. Traditionally seen primarily as devices with programmable gates, FPGAs have progressively evolved since year 2000 into "platform" devices with many integrated system-on-a-chip features, including components such as Ethernet MACs, DSP engines, microcontrollers, clock management circuitry, I/Os with reconfigurable signaling standards and terminations, and facilities supporting Bitstream encryption to prevent reverse engineering of designs.
This article expands the application areas covered by FPGAs by introducing a new class of primitives called "Soft PUFs." By exploiting the silicon uniqueness of each FPGA device and incorporating a special circuit (using existing FPGA fabric) to extract these "silicon biometrics", FPGAs can be used for new security-oriented applications that were not previously possible.
Physical Unclonable Functions
Physical Unclonable Functions (PUFs) are circuits that extract chip-unique signatures based on semiconductor fabrication variations that are very difficult to control or reproduce. These chip-unique signatures can be used to identify chips (a form of "silicon biometrics"), and can be used to generate "volatile" cryptographic keys. These keys disappear when the device is powered off; they can be bit-accurately restored, with aid of error correction, on subsequent power-ups.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- Security Chip Design Speeds on to Silicon
- Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions
- Developing FPGA applications for Edition 2 of the IEC 61508 Safety Standard
- Secure SOC for Security Aware Applications
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks