Common programming models for use on a dual-core processor
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- MPEG-4 is accelerated and footprint reduced by use of a configurable processor core
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Development and use of an Instruction Set Simulator of 68000-compatible processor core
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS