Common programming models for use on a dual-core processor
By Rick Gentile and David Katz, Analog Devices , Embedded.com
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
Mar 22 2006 (12:05 PM), Embedded.com
As embedded processors become more computationally capable, many new (and more advanced) algorithms can be ported, which in turn enable new applications. The most flexible architectures scale from low-end to high-end applications, enabling a common development platform across projects as well as providing more flexibility for development teams.
One way processor vendors provide the desired scalability with a single architecture is to include both single- and dual-core platforms. The goal with a multi-core processor is to allow nearly ideal scaling without overcomplicating the programming model. For example, in a dual-core system, the goal is to achieve as close to a 2x performance increase as possible.
In this paper, we will discuss the most common programming techniques for maximizing performance, as well as some system-related topics that commonly arise when porting to a dual-core processor.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UA Link DL IP core
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
Related Articles
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- MPEG-4 is accelerated and footprint reduced by use of a configurable processor core
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Development and use of an Instruction Set Simulator of 68000-compatible processor core
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection