Addressing the new challenges of ASIC/SoC prototyping with FPGAs

Ashok Kulkarni, S2C
EETimes (10/12/2011 1:04 PM EDT)

Introduction

Silicon process technologies have entered into the sub-30 nm realm, making it feasible to realize more than several billion transistors on a single chip. This, in turn, has made it possible to implement multiple extremely large and complex functions into a single SoC/ASIC/ASSP (hereafter referred to as SoC that applies to ASIC and ASSP) and conceive a myriad of applications catering to both consumer space and commercial usage. Furthermore, many consumer gadgets have a short life-cycle (some as low as 3 to 6 months) and are often differentiated by the software content that runs on them.

There are two primary requirements for a successful launch of these devices. First, the design must undergo thorough and comprehensive verification prior to the design tape-out. Second, an affordable hardware platform, representing the SoC prototype, for software development must be available prior to the arrival of first batch of silicon.

Silicon re-spin is not an option anymore as the mask cost alone runs into tens of millions of dollars and the lost market opportunity due to delayed product introduction may mean risking the business viability altogether.

This article first looks into various available solutions that can be used for functional verification and software development. It briefly compares various solutions and summarizes the pros and cons in using these solutions. The article focuses on FPGA-based prototyping and discusses various factors that must be taken into account to successfully implement a prototyping strategy.

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