Architectures and IP for SoC Clocking

By Krzysztof Kasiński and Jeff Galloway, Silicon Creations

Stringent performance requirements for the clocking systems (ultra-low jitter, low power, wide tuning range, and small form factor) mandate careful IP selection, design considerations, and optimization tradeoffs. Silicon Creations engineering team is involved from the beginning to help design SoC clock systems, from IP through distribution to the power delivery network.

Introduction
Content slide
About Silicon Creations
Silicon Creations in numbers
Silicon Creations IP in today SOCs
Optimized Clocking IP Portfolio
SoC Clocking Options using specialized SiCrIP
PLL Performance Matrix : Frequency, Area, Power
Jitter types by application
Sources of Jitter
Types of jitter : Period Jitter
Period Jitter & System Contributions
Types of Jitter : Long-Term Jitter (TIE)
Long-Term Jitter (TIE) & System Contributions
IP Engagement Process
Conclusion
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Semiconductor IP