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ultra-low voltage memory IP

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Compare 8 IP from 6 vendors (1 - 8)
  • Ultra-low voltage, SRAM
    • SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus. 
    • Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
  • Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
    • Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
    • Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
    • Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
    Block Diagram -- Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
  • Single Rail SRAM GLOBALFOUNDRIES 22FDX
    • Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
    • The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
    Block Diagram -- Single Rail SRAM GLOBALFOUNDRIES 22FDX
  • Dual-Rail SRAM Globalfoundries 22FDX
    • Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
    • Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
    Block Diagram -- Dual-Rail SRAM Globalfoundries 22FDX
  • ReRAM NVM in SkyWater 130nm
    • Weebit Resistive RAM (ReRAM) is a new type of Non-Volatile Memory (NVM) that is designed to be the successor to flash memory.
    • Weebit ReRAM IP can provide a high level of differentiation for System-on-Chip (SoC) designs, with performance, power, cost, security, environmental, and a range of additional advantages compared to flash and other NVMs.
    • Weebit’s first ReRAM IP product is available now in SkyWater Technology’s 130nm CMOS process (S130). The technology is fully qualified, available for integration in SkyWater’s users’ SoCs, and ready for production.
    Block Diagram -- ReRAM NVM in SkyWater 130nm
  • TLS 1.3 Compliant Crypto Coprocessor
    • NIST CAVP certified and OSCCA standard compliant crypto engine suite
    • Includes private/public key ciphers, message authentication code, hashes, and key derivation
    • Key wrapping function for the secure export of keys
    • Public-key coprocessor for digital signatures and key agreements over elliptic/Edward curves
    Block Diagram -- TLS 1.3 Compliant Crypto Coprocessor
  • Crypto Coprocessor
    • Comprehensively support all CPU architectures 
    • Crypto engine collective, consisting of private key cipher, message authentication code, hash, and  key derivation functions that are NIST CAVP certified and OSCCA standards compliant 
    • Key wrapping function aiding the export of keys for external use 
    Block Diagram -- Crypto Coprocessor
  • Ultra low power BLE 5.0 / ZigBee / Thread SoC - custom Modification, White Label chips
    • 32bit proprietary MCU: Better power performance then ARM M0 with max speed of 48Mhz
    • Memory: Program memory: 512kB Flash, 64kB on-chip SRAM with up to 32kB retention
    • RF transceiver: BLE 5.1 Compliant, 1Mbps, 2Mbps, Long Range 125kbps and 500kbps Or 2.4GHz proprietary 1Mbps/2Mbps/250kbps/500kbps mode with Adaptive
    • Frequency Hopping feature or 15.4 compliant, 250kbps
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