sureCore IP
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Ultra-low voltage, SRAM
- SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus.
- Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
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Ultra Low Power Embedded SRAM - Samsung 28FDSOI
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Power Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Power Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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In Memory Computing (IMC)
- CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data often has to be sent from an IoT device to a server for processing, which creates a connectivity requirement and an unavoidable latency.
- For time critical applications this is not acceptable and so there is a drive to do more computation within the device itself, i.e., AI processing at the Edge.
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Tuneable multi-port register file architecture - GF 12LP+
- Custom Register File Architecture
- Power savings >50%
- Wide operating voltage range