multi-processor graphics IP
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from 11 vendors
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64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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64-bit Multiprocessor with Level-2 Cache-Coherence
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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32-bit Multiprocessor with Level-2 Cache-Coherence
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA).
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Multiprocessor, 4-Way Simultaneous Multithreading
- Efficient Throughput
- Coherence Manager
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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- With Classifier, Look-Aside, 5-10 Gbps
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
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Processor Development Toolset
- A unified development model describing the processor in a single CodAL description
- High performance processor synthesis
- Complete UVM verification environment
- Advanced profiling and analysis
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Superscalar Out-of-Order Execution Multicore Cluster
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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Multi-Protocol Crypto Engine
- IPSec (IPv4 and IPv6):
- and 6379),
- MACsec
- 802.1AE
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Configurable CCIX controllers for CCIX 32G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
- Supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1 and 1.1 specifications
- Supports up to sixteen 32.0 25.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 128-, 256- or 512-bit datapath widths for maximum flexibility