multi-processor graphics IP
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64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 8 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA)
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64-bit Multiprocessor with Level-2 Cache-Coherence
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
- Floating point extension
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32-bit Multiprocessor with Level-2 Cache-Coherence
- AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
- It supports RISC-V standard ‘IMAC-FD’ extensions, Andes contributed DSP/SIMD 'P' extension (draft), user-level interrupt 'N' extension, and Andes performance/functionality enhancements such as instructions for faster memory accesses, faster branch handling, and Andes Custom Extension™ (ACE) to add user defined instructions.
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32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
- 900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU). With MMU, UX900 supports heavyload operating systems such as Linux. 900 Series can be applied to edge computing, data center, networking, etc.
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RVA23, Multi-cluster, Hypervisor and Android
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
- Private L2 cache support
- Level-3 shared cache and coherence support
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64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- 2 different packages with or without vector: AX46MPV, AX46MP
- in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
- Symmetric multiprocessing up to 16 cores
- Private Level-2 cache
- Shared L3 cache and coherence support
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32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
- It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
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32-bit Multiprocessors with Level-2 Cache-Coherence
- The A45MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch.
- It manages level-2 cache coherence including I/O coherence for cacheless bus masters.
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CXL - Enables robust testing of CXL-based systems for performance and reliability
- CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol. With features like protocol compliance checks, cache coherency validation, and advanced debugging tools, it ensures robust and efficient testing of high-performance computing systems.
- From HPC and AI to automotive and edge computing, CXL Verification IP supports diverse applications. It enables seamless communication between processors, memory, and accelerators, ensuring reliable performance in data centers, ML systems, cloud infrastructures, and telecom networks.
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Inline memory encryption engine, for FPGA
- Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
- Supports AES key sizes 128 or 256
- Internal key management with NIST-compliant key generation
- Encrypt memory space into user-defined vaults, each with a unique key
- Compatible with AMBA AXI4 interface
- Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
- Supports multiprocessor systems
