multi-processor graphics IP
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from 12 vendors
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64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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64-bit Multiprocessor with Level-2 Cache-Coherence
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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32-bit Multiprocessor with Level-2 Cache-Coherence
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA).
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CXL - Enables robust testing of CXL-based systems for performance and reliability
- CXL Verification IP is a cutting-edge solution for validating designs based on the Compute Express Link (CXL) protocol. With features like protocol compliance checks, cache coherency validation, and advanced debugging tools, it ensures robust and efficient testing of high-performance computing systems.
- From HPC and AI to automotive and edge computing, CXL Verification IP supports diverse applications. It enables seamless communication between processors, memory, and accelerators, ensuring reliable performance in data centers, ML systems, cloud infrastructures, and telecom networks.
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Inline memory encryption engine, for FPGA
- Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
- Supports AES key sizes 128 or 256
- Internal key management with NIST-compliant key generation
- Encrypt memory space into user-defined vaults, each with a unique key
- Compatible with AMBA AXI4 interface
- Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
- Supports multiprocessor systems
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Configurable CCIX controllers for CCIX 32G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
- Supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1 and 1.1 specifications
- Supports up to sixteen 32.0 25.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 128-, 256- or 512-bit datapath widths for maximum flexibility
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Superscalar Out-of-Order Execution Multicore Cluster
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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Processor Development Toolset
- A unified development model describing the processor in a single CodAL description
- High performance processor synthesis
- Complete UVM verification environment
- Advanced profiling and analysis
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32-Bit SPARC V8 Processor
- SPARC V8 instruction set with V8e extensions and compare-and-swap
- Advanced 7-stage dual-issue pipeline