XSPI IP
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12
IP
from 7 vendors
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10)
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xSPI - PSRAM Master
- SPI Protocol:
- AXI4 Slave
- AXI4 DMA Master
- AXI4 – LITE SLAVE
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xSPI NOR Flash controller
- Memory mapped access to the connected flash devices
- Continuous Burst transfer support
- Auto boot support
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xSPI Master IP | NOR IP
- JESD 251 compliant
- JEDEC SFDP Compliant
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xSPI Flash Memory Controller
- Compatible to most SPI protocols used by the NOR-Flash vendors including xSPI (JEDEC’s JESD251), and Xccela
- Single, Dual, Quad, Twin-Quad and Octal SPI lanes. Single and Dual Transfer Rate (STR and DTR)
- Programmable bit-length and number of SPI lanes used for command, address, latency (dummy cycle) and data. Programmable command encoding
- XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
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XSPI Controller IP
- Compliant with XSPI protocol of JEDEC standard version 1.0 specification
- Support single master and multiple slaves per interface port
- Support source synchronous clocking
- Support Deep power down enter and exit commands
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Secure-IC's Securyzr™ Inline Decrypter IP Core
- XIP (eXecution In Place) of encrypted code directly from Flash. (Optional xSPI controller)
- Decryption based on AES fully compliant with NIST FIPS 197
- AMBA Master/Slave interfaces
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AHB Subsystem
- Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as: BA2x, ARM Cortex-M0/M1M3/M4, and Several RISC-V processors
- AHB-SBS-BASE integrates: AHB Multi-Layer Interconnect, xSPI Controller, SRAM Controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
- AHB-SBS-EXT adds: Multichannel DMA, SPI-to-AHB bridge, and External parallel flash or SRAM controller
- Highly configurable and customizable
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QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
- Set of software accessible control registers to execute any Flash memory command
- Supports any device clock frequency, polarity and phase,
- Programmable baud rate generator,
- Built in FLASH Commands decoder supports most popular FLASH devices,
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SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- Set of software accessible control registers to execute any Flash memory command
- Supports any device clock frequency, polarity and phase,
- Programmable baud rate generator,
- Built in FLASH Commands decoder supports most popular FLASH devices,
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FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
- Set of software accessible control registers to
- execute any Flash memory command
- Support for most popular SPI like FLASH memories and PSRAM
- Supports any device clock frequency, polarity and phase