Video Processor IP
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HD Multi-window Video Processor IP Core
- This brief specification describes the operation of the HD Multi-window Video Processor (evaluation) IP Core.
- The IP Core is provided as a netlist in either EDIF, Verilog or VHDL formats.
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Flexible Pixel Processor Video IP
- The PP300 IP, is a flexible Pixel Processor that provides a wide range of processing functions.
- The PP300 IP offers various system integration options by providing either memory or direct pixel interfaces for input/output pixels.
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Neural Video Processor IP
- The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the advanced features and benefits of AI based video processing technologies.
- The NVP300 IP features an optimized hardware implementation to deliver real-time AI processing of 4K video whithin best-in-class silicon area and power budget suitable for embedded products.
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Mali-V76 Video Processor
- Multi-standard video processor
- 10/8-bit HEVC, VP9, VP8, H.264, AVS+/AVS and legacy
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Video Processor and Deinterlacer with Line-Doubled Output
- The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output.
- Additional functions include motion adaptive noise reduction, low angle directional interpolation and film cadence detection (supports multiple cadences including 3:2, 2:2 and others).
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Neuromorphic Processor IP (Second Generation)
- Supports 8-, 4-, and 1-bit weights and activations
- Programmable Activation Functions
- Skip Connections
- Support for Spatio-Temporal and Temporal Event-Based Neural Network
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RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing
- RTP/UDP/IP Protocol Hardware Stack, targets H.264 NAL Streams. See DB RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams
- For RX (i.e., receiving packets from the network), there is optional packet reordering to absorb network jitter.
- For both TX/RX, multiple NAL video streams supported. The DB-RTP-UDP-IP-NAL targets H.264 NAL Streams.
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High-Speed JPEG Video Encoder
- Speed and Area-Optimized encoder engine suitable for both still image and real-time video compression.
- 8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
- Supports any image resolution up to 64k x 64k.
- Suitable for still image and real-time video (streaming).
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ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
