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Video Processor IP

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Compare 174 IP from 48 vendors (1 - 10)
  • Mali-V76 Video Processor
    • Multi-standard video processor
    • 10/8-bit HEVC, VP9, VP8, H.264, AVS+/AVS and legacy
    Block Diagram -- Mali-V76 Video Processor
  • Video Processor and Deinterlacer with Line-Doubled Output
    • The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output.
    • Additional functions include motion adaptive noise reduction, low angle directional interpolation and film cadence detection (supports multiple cadences including 3:2, 2:2 and others).
    Block Diagram -- Video Processor and Deinterlacer with Line-Doubled Output
  • RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing
    • RTP/UDP/IP Protocol Hardware Stack, targets H.264 NAL Streams. See DB RTP-UDP-IP-AV for raw, uncompressed RGB/YUV video streams 
    • For RX (i.e., receiving packets from the network), there is optional packet reordering to absorb network jitter.
    • For both TX/RX, multiple NAL video streams supported. The DB-RTP-UDP-IP-NAL targets H.264 NAL Streams.
    Block Diagram -- RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing
  • High-Speed JPEG Video Encoder
    • Speed and Area-Optimized encoder engine suitable for both still image and real-time video compression.
    • 8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
    • Supports any image resolution up to 64k x 64k.
    • Suitable for still image and real-time video (streaming).
    Block Diagram -- High-Speed JPEG Video Encoder
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
  • ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
  • ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
  • ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
  • High-quality and powerful display processor
    • Support 8K@60FPS or multiple 4K@120FPS
    • All common HDR formats, including HDR10, HDR10+ and HLG
    • Security Features for Content Protections
    • Subjective and objective image quality
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